Case Study: Small Business Consumer Products Company


  • Needed to address the following challenges with memory compilers:
    • Meet aggressive power targets
    • Meet aggressive area targets
    • Reduce development cost
    • Obtain high yield
    • Improve availability of IP in target foundry process
    • Reduce project risk

Use Case

  • Used Synopsys’ DesignWare Memory Compilers at 65-nm LP process node.
  • Implemented the following functions containing DesignWare Memory IP:
    • CPU cores (e.g., ARM, MIPS, ARC, etc.)
    • Other blocks of the SoC


  • Purchased Synopsys’ DesignWare Memory Compilers due to:
    • Completeness of solution (memory, BIST, repair, post-silicon debug)
    • Availability on required process node(s)
    • Previous experience with Synopsys IP
  • Rated DesignWare Memory Compiler as differentiated on all of the following attributes:
    • Speed
    • Power consumption
    • Area
    • Features/capabilities
    • Silicon validation
    • Ease of integration
    • Completeness of solution (memory, BIST, repair, post-silicon debug)
  • Achieved a 10-29% improvement in dynamic power, leakage power and area with DesignWare Memory Compilers.
  • Achieved a 1 – 10% increase in performance with DesignWare Memory Compilers.
  • Realized the following benefits with DesignWare Memory Compilers:
    • Achieved first-pass silicon success
    • Met design’s performance, power and area goals
    • Reduced development cost


“DesignWare Embedded Memories are a complete solution with a single integration environment.”

TechValidate Survey of a Small Business Consumer Products Company

About This Data

This data was sourced directly from verified users of Synopsys DesignWare IP by TechValidate.

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Validated on Oct 09, 2013

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